`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/26 22:40:41
// Design Name: 
// Module Name: M_W
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module M_W(
    input logic             clk,res,
    input logic             clr,

    input logic [31: 0]     pc_m,
    input logic             memtoreg_m,
    input logic             regwrite_m,
    input logic [31: 0]     res_m,
    input logic [31: 0]     read_data_m,
    input logic [ 4: 0]     write_reg_m,
    input logic [ 1: 0]     hilowrite_m,
    input logic [63: 0]     hilo_o_m,

    output logic [31: 0]    pc_w,
    output logic            memtoreg_w,
    output logic            regwrite_w,
    output logic [31: 0]    res_w,
    output logic [31: 0]    read_data_w,
    output logic [ 4: 0]    write_reg_w,
    output logic [ 1: 0]    hilowrite_w,
    output logic [63: 0]    hilo_o_w
    
    );

    always @(posedge clk) begin
        if (res) begin
            pc_w            <= 32'b0;
            memtoreg_w      <= 1'b0;
            regwrite_w      <= 1'b0;
            res_w           <= 32'b0;
            read_data_w     <= 32'b0;
            write_reg_w     <= 5'b0;
            hilowrite_w     <= 2'b0;
            hilo_o_w        <= 63'b0;
        end
        else if(clr) begin
            pc_w            <= 32'b0;
            memtoreg_w      <= 1'b0;
            regwrite_w      <= 1'b0;
            res_w           <= 32'b0;
            read_data_w     <= 32'b0;
            write_reg_w     <= 5'b0;
            hilowrite_w     <= 2'b0;
            hilo_o_w        <= 63'b0;
        end 
        else begin
            pc_w            <= pc_m;
            memtoreg_w      <= memtoreg_m;
            regwrite_w      <= regwrite_m;
            res_w           <= res_m;
            read_data_w     <= read_data_m;
            write_reg_w     <= write_reg_m;
            hilowrite_w     <= hilowrite_m;
            hilo_o_w        <= hilo_o_m;
        end
    end
endmodule
